Sr. R&D SW Developer
Bay Area #5291
My client is a successful Start-up (but way more than a Start-up), that develops verification IP targeting specific protocols such as PCIe, NVMe, etc. They seek a Strong coder in System Verilog and UVM to help in the development of this companies’ VIP's. The right candidate will have significant knowledge with Memory design, (preferably worked on memory controller) on an SOC...DDR4 preferred...(Variations will be considered).
A Strong understanding of engineering process and discipline is essential. Knowledge of SystemVerilog and UVM is the key requirement.
5+ years of SystemVerilog/UVM verification experience…
Must have experience in developing SystemVerilog/UVM based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage.
Must have strong UVM/SystemVerilog coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, Questaused in Verification and waveform based debugging tools.
Experience with commercial VIPs and UVM verification methodology is required.Working knowledge and experience of one or more of the connectivity protocols such as PCIe, MIPI, USB, NVMe, DDR4, ONFI, HBM, UFS, Unipro, eMMC, Ethernet, SATA, Scripting helpful...
Exposure to IP design and verification processes including VIP development is an added advantage.
Mandarin is a requirement to work with team in Taiwan…The R&D team frequently works on customer engagements so decent English communication skills are important.