Senior and (less) Senior Design Verification Engineers

Austin #5316 and #5318

My client is looking for someone to contribute to the backbone of some of the world's most popular SoCs? You will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs. You'll create and work with existing verification methodologies for their designs that are developed in languages that blend traditional RTL with leading-edge software, to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine.


  • Advanced UVM based testbench development and debugging

  • Define, document, develop and execute RTL verification test/coverage at sys level

  • Performance verification and power-aware verification

  • Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog 

  • Help improve and refine verification process, methodology, and metrics

  • UVM expertise on complex SoC projects from test bench development to verification closure

Skills and Qualifications:

  • 7+ years of design and verification experience, (3-5 for less Senior)...a plus in interconnect verification experience

  • Verification flow enhancements using scripting language such as Shell, Python & JavaScript

  • Strong RTL (Verilog) and UVM/C test bench debugging skills

  • Experience integrating vendor provided VIPs for unit and system level verification

  • Experience with Arm AMBA protocols

  • This opportunity involves high performance, low power designs on a highly visible project

 H-1b transfers accepted

(Attach Resume)

Tel. 305-598-2222

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