Physical Design (PD) Hardware Engineer    Bay Area or Austin, TX  #5377

This client is looking for an experienced PD Hardware Engineer who wants to contribute to the backbone of some of the world's most popular SoCs. You will brings intelligence, motivation, and sense of humor to an expert team to design and deliver interconnect & memory hierarchy solutions, for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs. You'll go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be a part of a proven-successful start-up, and to influence development environment, architecture, verification, and everything in-between and not just be stuck in a silo or just a cog in the machine.

 

Required:

  • 7 plus years of experience in ASIC/SoC back end design

  • In-depth knowledge of physical design constraints for multi clock and multi power domain designs 

  • In-depth knowledge of running synthesis and creating floor plans based on data flow

  • Understanding of the complete tool-flow from RTL to netlist

  • Experience with Synopsys back end tools

  • A track record of delivering successful SoCs at 16nm or below

  • A passion for using software to accelerate RTL design   

 

Desired Skills:

  • You have experience with scripting languages such as TCL/Perl/Phyton etc. 

  • You have experience with automation of back end flows 

  • You have experience with SRAM compilers 

  • You have worked with Cadence back end tools

(Attach Resume)

Tel. 305-598-2222

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