HLS Verification Architect  

Several Areas #5567A-D

My client is an internationally respected and recognized public company.  They are seeking a highly motivated individual who will be a senior member of the technology staff for the HLS technical marketing team. The technical marketing team plays a key role as the technical experts supporting and driving new methodologies of verification in raising the design/verification abstraction to C and driving the rapid growth of their High-Level Synthesis products. The position works closely with both a dedicated FAE and Sales team and directly with customers to help solve problems, interface into R&D as a customer advocate and serve as world-wide technical expert. The ideal candidate is deeply technical with extensive experience in ASIC verification and/or ASIC design, has strong communication skills, experience working with customers and is self-motivated and can work independently. Travel required.

Responsibilities:

  • Work with the HLS, Formal, Verification R&D and technical teams and tools to understand, help architect and drive the next generation methodology for verification for HLS (High-Level Synthesis); debug, verification and C to RTL verification closure.

  • Use your verification experience to work directly with their HLS customers (both experienced and new to HLS) to understand their current verification methodology and their current use of HLS and any verification challenges to both bring their input into the methodology and to work on solutions to solve their problems.

  • Work with R&D and product marketing to collaboratively drive user requirements gathered from your experience, input from customers and field engineers to drive the functionality, ease of use and scalability into their tools .

  • Create and deliver various example designs and reference flows that demonstrate the HLS/HLV verification methodology using both dynamic and formal that will be used with the field technical and customers as reference examples and teaching guidelines.

  • Create and deliver technical training for experienced AE’s and customers in addition to technical white papers, application notes and technical presentations.

  • Create and deliver technical collateral such as technical papers, conference presentations/papers and technical webinars and seminars helping to promote and drive industry understanding of HLV methodology

  • Lead agile teams with R&D for various verification tools such as Coverage, Design-Checking, Formal with a focus on requirements and deliverables

Required Qualifications

  • BS/MSEE or related field experience required

  • Solid background in RTL verification for ASIC/FPGA with 10+ years relevant work experience

  • Solid understanding of various verification techniques including dynamic and formal including System Verilog, UVM, ABV, property checking, etc.

  • Knowledge of C++ and/or SystemC and object-oriented design preferred

  • Experience with HLS preferred

  • Experience with ASIC RTL synthesis tools (Design Compiler, RTL Compiler, etc) preferred

  • Demonstrated strength in problem solving skills

  • Extremely strong communication skills and proven track-record of working collaboratively with both R&D technical team and other marketing and sales

  • No travel restrictions

  • Strong presentation, verbal and written communication skills

Travel: Travel including some international travel will be required

(Attach Resume)