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Senior R&D Engineer Timing Closure Specialist

Armenia / Europe #6404

Our client is a privately funded EDA (Electronic Design Automation) company established in 2009, focused on developing software solutions addressing Timing constraints generation and verification; CDC analysis and verification, Clock Tree analysis and RTL floorplanning.  They are headquartered in California, with their main R&D center in Europe. They are open to qualified candidates working remotely in the region.  With a stat-up mentality, they are known for solving Timing Closure, Timing Constraints problems from RTL to GDS2. They know that Timing closure and Timing constraints are huge problems and this company has complete working end to end, front to back solutions. SDC is the end game and it is their goal to make sure that the SDC is clean and ready for tape out. They have a working environment that is conductive to learning new technologies and contributing to solutions of very challenging problems in the VLSI design automation space.

They need skilled ASIC VLSI Engineers with a good physical flow background to help build and improve their product. The right candidate must be a strong SW Programmer with a minimum of about 3-years-experience, that has worked with ASIC Digital Physical Flows and is strong in timing closure issues.  You will edit timing constraints in Primetime, possibly use QT for their GUI’s, and of course, C++ for programming.  TCL and/or PERL is essential as well.  

Experience Requirements / Qualifications:

The right full-time candidates will have the following requirements:
- A successful candidate must have a solid experience and knowledge of C++. good familiarity with advanced data structures (maps, sets, trees) and algorithms especially good knowledge of graph algorithms (traversals, min/max paths, spanning trees, etc.) and their time and space complexities.


  • Knowledge of Qt framework (GUI, Core, Concurrent) and the standard C++11 libraries needed. Development experience under Linux using GNU tool-chain / Git is a plus

  • Familiarity with Tcl scripting and ASIC design flow (Verilog/VHDL, synthesis, STA) will be a big plus but is not a hard requirement. 

  • Knowledge of formal analysis frameworks and algorithms, such as Binary Decision Diagrams (BDD) and SAT solvers will also be a plus, but is not a requirement.

In this role, your input is critical.  You will interact with the R&D management and team (based in USA and elsewhere) as well as directly with customers. A good command of both spoken and written English is required.

Computer Science/Engineering Bachelor’s Degree or similar is required.

Some travel to customers in Europe, Israel, USA and Japan (1-2 times per year for a few days) may be required.

(Attach Resume)

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