I have a hot startup doing Edge Processors, AI software and hardware and has already taped out their first chip. This client is an exciting new company that just closed on a sizable Series C Funding package, and they need DFT Engineers. This company is at the forefront of hardware technologies accelerating and optimizing FHE encryption via Artificial Intelligence. They expect to see performance gains in several orders of magnitude which will transform the 300B + Cloud market by ensuring security and stability of data transmission. 

They are seeking a few seasoned DFT Engineers with a minimum 7-15 years of experience to join their ASIC team. The right candidates will have prior experience in defining DFT Architecture and how to execute on the DFT implementation plan, defining the methodology, setting up the environment and driving the Synthesis/Formal Implementation flows in a Hierarchical DFT environment. Comprehensive understanding of the issues faced between the RTL, DFT and the Physical design Teams. Good understanding of clocking structures and tradeoffs between Power, Area and Timing.

 

Skills Needed

• Expertise is SDC and Verilog is mandatory. 

• Leading ASIC infrastructure, defining methodology, driving the DFT flows.

• Expertise in ACJTAG/BSD/1500 wrappers

• Expertise in Scan/ On chip Clocking/@speed Test (TDF) /Path Delay

• Prior experience with Serializers and In-system Scan

• Strong experience in ECO methodology.

• Driving Backend Test generation and wafer/ATE Test with external Vendors.

• Work with hardware Team to promote SDC’s in a multi-level Physical hierarchical design. (Hierarchical DFT/Test) and with Physical design Time to refine constraints.

• Work with Timing team, consolidate Timing Modes, STA experience desired.

• PERL /TCL programming ability required.

• Prior tapeout experience required in a 16nm environment or smaller.

• Strong communication and presentation skills.

• BSEE/MSEE is required.

 

Benefits package- 401k, Medical, Dental, Vision etc

 

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