Mixed Signal Verification Engineer
East Coast or Remote #6011
My client is experiencing strong growth as they design and develop high performance analog and mixed signal ICs. They seek a strong, experienced engineer that has worked on Verification of mixed signals. In this role, you will further develop, enhance, and work within the Analog Mixed-Signal (AMS) and Digital Mixed-Signal (DMS) Verification environments. Help establish UVM environments on projects to bring the AMS and DMS development flows into a single verification infrastructure. Collaborate with the Design Lead on projects to create models and verify the top-level designs. This role will report to the Director of Design.
Roles & Responsibilities:
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Create the UVM environment for projects including AMS and DMS development flows
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Generate System Verilog and Verilog-A models
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Collaborate with the Design Lead and other Analog and Digital designers to ensure they can use and update models and run simulations where needed
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Top level and multi-block mixed signal design verification using Cadence simulation tools
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Write clear model documentation
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Drive continuous improvement opportunities that will boost design verification quality and efficiency
Requirements:
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BSEE; MSEE preferred
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6+ years of professional experience modeling analog and mixed-signal ICs and running top level simulations
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Strong knowledge of most analog cells and analog integrated circuit design concepts and fundamentals to ensure models accurately represent circuit behavior
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Proficient in Cadence mixed signal simulation tools
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Strong knowledge of Verilog, Verilog-A, Verilog-AMS and System Verilog
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Scripting (Perl, Python, or other)
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Knowledge and experience in product development from definition to tapeout
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Strong communication and analytical skills
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