Mixed Signal Verification Engineer 

East Coast or Remote #6011

My client is experiencing strong growth as they design and develop high performance analog and mixed signal ICs. They seek a strong, experienced engineer that has worked on Verification of mixed signals. In this role, you will further develop, enhance, and work within the Analog Mixed-Signal (AMS) and Digital Mixed-Signal (DMS) Verification environments. Help establish UVM environments on projects to bring the AMS and DMS development flows into a single verification infrastructure. Collaborate with the Design Lead on projects to create models and verify the top-level designs. This role will report to the Director of Design.

 

Roles & Responsibilities:

  • Create the UVM environment for projects including AMS and DMS development flows

  • Generate System Verilog and Verilog-A models

  • Collaborate with the Design Lead and other Analog and Digital designers to ensure they can use and update models and run simulations where needed

  • Top level and multi-block mixed signal design verification using Cadence simulation tools

  • Write clear model documentation

  • Drive continuous improvement opportunities that will boost design verification quality and efficiency

 

Requirements:

  • BSEE; MSEE preferred

  • 6+ years of professional experience modeling analog and mixed-signal ICs and running top level simulations

  • Strong knowledge of most analog cells and analog integrated circuit design concepts and fundamentals to ensure models accurately represent circuit behavior

  • Proficient in Cadence mixed signal simulation tools

  • Strong knowledge of Verilog, Verilog-A, Verilog-AMS and System Verilog

  • Scripting (Perl, Python, or other)

  • Knowledge and experience in product development from definition to tapeout

  • Strong communication and analytical skills

 

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