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Member of Technical Staff - Design & Verification Training

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About the Role

Design and develop training courseware
Deliver all product and service training via classroom, virtual or webinar.
Provide customized training to meet client requirements.

Maintain all developed courseware and tutorial scripts.

Travel to customer sites mostly within North America but occasionally worldwide (mostly virtual).
Sustain your knowledge at the leading edge of hardware/systems design/verification languages/tools/methods.
Involvement in technical marketing activities and technical support to the sales process

Requirements

ALL CANDIDATES MUST HAVE

Expert-level knowledge and experience in ASIC/FPGA design and verification using SystemVerilog & UVM

IDEAL candidate also has expert-level knowledge and experience in ASIC/FPGA design and verification using VHDL and/or Formal and has ideally provided classroom training and/or digital design or verification consulting services. Excellent communication skills are a must. You express confidence and are adept and enthusiastic about elevating students' knowledge.

Excellent professional written, verbal, and presentation communication skills.

Experienced using tools from Cadence, Siemens EDA, and Synopsys

Estimated level of travel is <25%

BS of Science Degree in Electrical Engineering or Computer Science, MS preferred

About the Company

My client is one of the largest companies offering Semi-related training worldwide. They seek an experienced ASIC/FPGA design & verification technical leader to join a fast paced, team-oriented environment where you can make a positive impact on the engineers you train. You should have the ability to update and develop training curriculum, effectively engage an audience and present complex engineering topics in a clear, easily absorbed way.

This is an exceptional opportunity for an engineer ready to teach others their years of experience, an opportunity to raise your visibility in the design and verification community. You like helping others gain knowledge of complex topics such as VHDL, Verilog, SystemVerilog, UVM, SystemC, TLM, Formal and other emerging design and verification languages through instructor-led classroom and virtual training venues.

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