About the Role
Design and model memory architectures and memory hierarchies using C/C++ for simulation.
Optimize memory performance through innovative techniques, including cache coherency improvements and prefetching strategies.
Collaborate with cross-functional teams to enhance system-level cache architectures and interconnect designs.
Conduct pre-silicon performance modeling and validation to predict and mitigate potential bottlenecks.
Develop advanced cycle-accurate simulations for memory components and evaluate performance metrics.
Requirements
Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field; Ph.D. preferred.
Extensive experience in memory design, specifically with SoC architecture and memory subsystems.
Proficient in programming languages C, C++, Python, and experience with modeling and simulation tools.
Strong understanding of cache coherency protocols (e.g., CHI, MESI/MOESI) and on-chip interconnects
Proven ability to analyze SoC performance regarding bandwidth and latency.
Preferred Experience:
Experience with SRAM optimization and memory-controller design.
Familiarity with cycle-accurate simulation and RTL validation methods.
Background in data prefetching algorithms and techniques, particularly in high-performance computing environments.
About the Company
My client is a well-funded, exceptionally well managed experienced team Start-Up looking for a highly skilled Performance Engineer specializing in SRAM memory design. The ideal candidate will possess in-depth knowledge of memory architecture, cache coherency, and performance optimization. This role demands a strong engineering background and a passion for driving efficiency in memory subsystems. This is a great Founding Engineering opportunity. Compensation is commensurate with levels of experience.