About the Role
Collaborate with AI engineers to model and codify chip design and verification workflows.
Design, implement, and debug RTL designs and SystemVerilog/UVM testbenches used in training and validating AI agents.
Provide deep domain expertise to help AI agents interpret specifications, generate RTL code, and understand verification coverage.
Build reusable examples, design patterns, and edge cases to train and evaluate generative and agentic AI models.
Support benchmarking and evaluation of AI-assisted design and verification productivity across realistic chip development tasks.
Work closely with customers, product, and research teams to translate engineering pain points into automated AI workflows.
Requirements
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in RTL design, functional verification, and/or architecture-level modeling.
Proficiency with Verilog/SystemVerilog, UVM, and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa).
Experience designing and verifying complex subsystems or SoCs, preferably in production or research tapeouts.
Familiarity with lint, CDC, formal, coverage analysis, and synthesis flows.
Interest or experience in AI/ML, especially AI-assisted engineering tools, a plus.
Strong collaboration skills; a passion for enabling the next gen EDA workflows.
Competitive salary, meaningful equity, benefits, and growth opportunities.
About the Company
This company is reinventing semiconductor with founders that are the leading experts in AI and chip design and are working with top-20 semiconductor companies, major cloud providers, and next-generation hardware startups.