Senior Staff Verification Engineer
Location Open #5812
I have a hot startup doing Edge Processors, AI software and hardware and has already taped out their first chip. This client is an exciting new company that just closed on a sizable Series C Funding package, and they need DFT Our client is an exciting new company that just closed on a sizable Series C Funding package, and they are in need of Senior Verification Engineers. This company is at the forefront of hardware technologies accelerating and optimizing FHE encryption via Artificial Intelligence. They expect to see performance gains in several orders of magnitude which will transform the 300B + Cloud market by ensuring security and stability of data transmission.
They are looking for a seasoned lead Verification Engineer with a minimum of 10+ year of experience to join their verification team. The right candidate will have prior experience with verification flows, building efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full lifecycle of verification, from verification planning and test execution, to collecting and closing coverage and be able to define the verification infrastructure, set up the environment and drive the Functional Verification flow.
Expertise in UVM and System Verilog is mandatory.
Expertise in functional coverage flows, property checking and Assertions.
Prior experience with VIP of multi-protocol Serdes.
Prior experience with formal verification.
Prior experience with Protocol verification such as Ethernet, PCIe, DDR, System Interconnect (NOC, NIC).
Strong communication and presentation skills.
BSEE/MSEE is required.
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